1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device. In particular, embodiments of the invention relate to a nonvolatile semiconductor memory device comprising a U-shaped floating gate electrode and a method for fabricating the nonvolatile semiconductor memory device.
This application claims priority to Korean Patent Application No. 10-2005-0068566, filed on Jul. 27, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
A semiconductor memory device is used for storing data and may be generally classified as either a volatile memory device or a nonvolatile memory device. Data may be written to and read from a volatile memory device while power is supplied to the volatile memory device, but stored data is lost when power is not supplied to the volatile memory device. However, a nonvolatile memory device may retain stored data even when power is not supplied to the device. Thus, nonvolatile memory devices are widely used in various other electronic devices, such as a memory cards used to store music or image files, in case power cannot be continuously supplied to the memory devices in those electronic devices.
FIG. (FIG.) 1 is a plane view of a portion of a conventional nonvolatile semiconductor memory device.
Referring to FIG. 1, device isolation patterns 1 disposed on the substrate are disposed adjacent to and on opposite sides of an active region of a substrate. A floating gate electrode 2 is formed on the active region between adjacent device isolation patterns 1, and a control gate electrode 3 is disposed over floating gate electrode 2. A gate insulating layer (not shown) is interposed between the substrate and floating gate electrode 2, and a gate interlayer insulating layer (not shown) is interposed between floating gate electrode 2 and control gate electrode 3.
Data is stored in floating gate electrode 2. That is, a memory cell stores a data value of logic “0” when charge is not stored in floating gate electrode 2, while the memory cell stores a data value of logic “1” when the charge is stored in floating gate electrode 2. Programming and erase operations are performed by applying operational voltages to control gate electrode 3. When an operational voltage is applied to control gate electrode 3, a predetermined voltage is induced on floating gate electrode 2. An electric field created by the induced voltage may cause charge to penetrate through the gate insulating layer by Fowler-Nordheim tunneling or hot carrier injection.
The ratio of the voltage induced on floating gate electrode 2 to the operational voltage applied to control gate electrode 3 is referred to as a coupling ratio. As the coupling ratio in a semiconductor memory device increases, the power consumption of the device may be reduced because the voltage level of the operational voltage can be reduced. One method for increasing the coupling ratio in a semiconductor memory device is increasing the capacitance between control gate electrode 3 and floating gate electrode 2. It may be possible to increase an surface area over which control gate electrode 3 and floating gate electrode 2 overlapped with one another in order to increase the capacitance between control gate electrode 3 and floating gate electrode 2. However, as semiconductor memory devices become more highly integrated, the opportunity to increase the surface area over which control gate electrode 3 and floating gate electrode 2 overlap is limited because of space restrictions within the semiconductor memory devices.